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ADE7518
INTERRUPT FLAGS
The interrupt flags and status flags associated with the interrupt vectors are shown in Table 62 and Table 63. Most of the interrupts have
flags associated with them.
Table 62. Interrupt Flags
Interrupt Source
IE0
TF0
IE1
TF1
RI + TI
TF2 + EXF2
IPSM (Power Supply)
IADE (Energy Measurement DSP)
Flag
TCON.1
TCON.5
TCON.3
TCON.7
SCON.1
SCON.0
T2CON.7
T2CON.6
IPSMF.6
MIRQSTL.7
Bit Name
IE0
TF0
IE1
TF1
TI
RI
TF2
EXF2
FPSM
ADEIRQFLAG
Description
External Interrupt 0.
Timer 0.
External Interrupt 1.
Timer 1.
Transmit Interrupt.
Receive Interrupt.
Timer 2 Overflow Flag.
Timer 2 External Flag.
PSM Interrupt Flag.
Read MIRQSTH, MIRQSTM, MIRQSTL.
Table 63. Status Flags
Interrupt Source
ISPI/I2CI
IRTC (RTC Interval Timer)
WDT (Watchdog Timer)
Flag
SPI2CSTAT 1
SPI2CSTAT 1
TIMECON.7
TIMECON.2
WDCON.2
Bit Name
N/A
N/A
MIDNIGHT
ALARM
WDS
Description
SPI Interrupt Status Register.
I 2 C Interrupt Status Register.
RTC Midnight Flag.
RTC Alarm Flag.
Watchdog Timeout Flag.
1
There is no specific flag for ISPI/I2CI; however, all flags for SPI2CSTAT need to be read to assess the reason for the interrupt.
A functional block diagram of the interrupt system is shown in
Figure 75. Note that the PSM interrupt is the only interrupt in
the highest priority level.
If an external wake-up event occurs to wake the ADE7518 from
PSM2, a pending external interrupt is generated. When the EX0
or EX1 bit in the Interrupt Enable SFR (IE, 0xA8) is set to enable
external interrupts, the program counter is loaded with the IE0
or IE1 interrupt vector. The IE0 and IE1 interrupt flags in the
TCON register are not affected by events that occur when the
8052 MCU core is shut down during PSM2. See the Power
Supply Management (PSM) Interrupt section.
The RTC and I 2 C/SPI interrupts are latched such that pending
interrupts cannot be cleared without entering their respective
interrupt service routines. Clearing the RTC midnight flags and
alarm flags does not clear a pending RTC interrupt. Similarly,
clearing the I 2 C/SPI status bits in the SPI Interrupt Status SFR
(SPISTAT, 0xEA) does not cancel a pending I 2 C/SPI interrupt.
These interrupts remain pending until the RTC or I 2 C/SPI
interrupt vectors are enabled. Their respective interrupt service
routines are entered shortly thereafter.
Figure 75 shows how the interrupts are cleared when the interrupt
service routines are entered. Some interrupts with multiple
interrupt sources are not automatically cleared; specifically, the
PSM, ADE, UART, and Timer 2 interrupt vectors. Note that the
INT0 and INT1 interrupts are only cleared if the external interrupt
is configured to be triggered by a falling edge by setting IT0 in
the Timer/Counter 0 and Timer/Counter 1 Control SFR (TCON,
0x88). If INT0 or INT1 is configured to interrupt on a low level,
the interrupt service routine is re-entered until the respective
pin goes high.
Rev. 0 | Page 76 of 128
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